This invention relates to integrated circuits, and in particular to the comparison and selection of the greater of two voltage signals in an integrated circuit.
FIG. 1 is a simplified block diagram showing a non-volatile memory (NVM) device 100, which represents one type of integrated circuit that utilizes multiple voltage sources. NVM device 100 includes an array 110 of NVM cells 115, and peripheral control circuitry located around array 110 including an input/output (I/O) control circuit 120, a word line control circuit 130, an optional address decoder 135, a bit line control circuit 140, a bit line (Y) decoder 145, and a sense amplifier circuit 150. NVM cells 115 are arranged in rows and columns such that each row of NVM cells 115 is connected to an associated word line WL0 through WL8, and each column of NVM cells 115 is connected to two associated bit lines BL0 through BL8.
Operation of NVM device 100 will now be described in detail with reference to FIG. 1. Data, address (ADDR), and control (R/W/E) signals are transmitted through I/O control circuit 120 during read, write, and erase operations. During write operations, address data and an associated data word are respectively transmitted via I/O control circuit 120 to word line control circuit 130 (via optional address decoder 135) and to bit line control circuit 140. Word line control circuit 130 uses the address data to pass an appropriate programming voltage onto an associated word line (e.g., word line WL0), and bit line control circuit 140 then drives selected bit lines using an appropriate programming voltage to program selected NVM cells 115 of the selected row. According to one convention, the NVM cells 115 that are programmed store a logic xe2x80x9c1xe2x80x9d data value, and those NVM cells that remain unprogrammed store a logic xe2x80x9c0xe2x80x9d data value. During subsequent read operations, address data associated with selected data word is transmitted via I/O control circuit 120 to write line driver circuit 130, which uses the address data to apply an appropriate read voltage on the associated word line (e.g., word line WL0), thereby causing the selected data word to be read from the NMV cells onto bit line BL0 through BL7. The thus-read data word is then transmitted via Y-decoder 145 to sense amplifier circuit 150, which in turn passes the selected data word to I/O control circuit 120 for transmission out of NVM device 100. Finally, during erase operations, the word lines and bit lines are maintained at an appropriate voltage level that causes all programmed NVM cells 115 to be erased. Those of ordinary skill in the art will recognize that the above explanation is greatly simplified, and that many variations in the described operations are possible.
Referring to the upper left corner of FIG. 1, in addition to the peripheral control circuitry described above, NVM device 100 includes voltage sources 160 and 170 that respectively generate a first (read) voltage signal V1 and second (program) voltage signal V2, which are transmitted to word line control circuit 130 and bit line control circuit 140. Voltage signals V1 and V2 are selectively passed by these control circuits to the bit lines and word lines in order to facilitate the read and program/erase operations mentioned above.
FIG. 2 is a simplified circuit diagram showing a portion of word line control circuit 130 in additional detail. Word line control circuit 130 includes a conventional voltage control circuit 132 and a word line driver 136 that are used in combination to couple an associated word line WL to first voltage signal V1, second voltage signal V2, or ground (i.e., zero Volts). Voltage control circuit 132 includes a first PMOS transistor 133 connected between the first voltage source (i.e., voltage source 160, see FIG. 1) and an output node 134, and a second PMOS transistor 135 connected between the second voltage source (i.e., voltage source 170, see FIG. 1) and output node 134. Note that PMOS transistor 133 is controlled by second voltage signal V2, and PMOS transistor 135 is controlled by first voltage signal V1. Word line driver 136 includes a PMOS transistor 137 and an NMOS transistor 138 that are connected in series between output node 134 of voltage control circuit 132 and ground. PMOS transistor 137 and NMOS transistor 138 are controlled by a word line control signal VIN. During operation, voltage control circuit 132 passes a maximum voltage VMAX, which is the greater (i.e., most positive voltage) of first voltage signal V1 and second voltage signal V2, to driver 136, which in turn applies either VMAX or ground onto word line WL in accordance with word line control signal VIN.
A problem with conventional voltage control circuit 132 arises when voltage signals V1 and V2 are within one threshold voltage of each other. In particular, referring to FIG. 2, when voltage signals V1 and V2 vary by less than one threshold voltage of PMOS transistors 133 and 135, then both of these transistors remain turned off and output node 134 remains floating, thereby potentially causing a latch up condition, and possibly causing damage to NVM device 100 by coupling voltage sources 160 and 170 together. This problem arises, for example, when voltage signals V1 and V2 are asynchronously changed between relatively low voltages used to perform read operations, and relatively high voltages utilized during program/erase operations. That is, when voltage supply 160 changes voltage signal V1 between a read voltage level and a program voltage level, depending upon the current operation, and voltage supply 170 similarly changes voltage signal V2 between a read voltage level and a program voltage level, and voltage supplies 160 and 170 operate asynchronously, then several situations can arise in which these voltage signals are within one threshold voltage of each other, as set forth in the following example.
FIG. 3 is a timing diagram showing exemplary voltage signals V1 and V2 that produce the problem mentioned above. In particular, FIG. 3 shows voltage signals V1 and V2 during a read (normal) operation (e.g., time T0 through T2) and a subsequent program operation. During read operations, voltage signal V1 is selectively adjustable (trimmable) by a user/manufacturer to be within a voltage range between a maximum value VREADxe2x80x94MAX (e.g., system voltage VDD plus one Volt) and a minimum value VREADxe2x80x94MIN (e.g., system voltage VDD minus one Volt). At the same time, voltage V2 is maintained at system voltage VDD. That is, depending on how V1 is trimmed, during read operations voltage signal V1 may be higher or lower than voltage signal V2. Conversely, during program operations (e.g., time T2 through T5), voltage signal V1 is raised to a program verify voltage VVERIFY (e.g., VDD plus two or more Volts), and voltage V2 is raised to a program voltage VPROGRAM (e.g., 10 Volts). Of course, during a subsequent read operation, voltage signals V1 and V2 return to their previous read levels, as indicated after time T5. As described above, voltage signals V1 and V2 are selectively utilized by bit line control circuit 140 to control the bit lines BL0-BL8 of NVM device 100, and are transmitted to conventional voltage control circuit 132 of word line control circuit 130 (see FIG. 2).
In the example indicated by the timing diagram in FIG. 3, there are several situations in which first voltage signal V1 and second voltage signal V2 xe2x80x9ccross overxe2x80x9d (i.e., signal V1 changes from being lower than signal V2 to being higher than signal V2, or vice versa) or are otherwise within one threshold voltage of each other, which can cause PMOS transistors 133 and 135 of conventional voltage control circuit 132 (see FIG. 2) to erroneously turn off. First, voltage signal V1 may be erroneously trimmed to a read level that is within one threshold voltage of VDD (i.e., the read level of voltage signal V2). Second, as indicated at time T1, read cycle charging of an associated word line using voltage signal V1 can cause a temporary drop in voltage signal V1, thereby causing voltage signal V1 to temporarily equal voltage signal V2. Third, during the transition between a read operation and a program operation (time T2 to T4), a cross-over occurs at a time T3 when voltage signal V1 reaches the program verify voltage VVERIFY before voltage signal V2 reaches the program voltage VPROGRAM. Similarly, during a subsequent transition from the program voltage levels to the read voltage levels (time T5 on), a cross-over can occur at a time T6 when voltage signal V2 drops below the program verify voltage VVERIFY before voltage signal V1 drops back to its read level.
What is needed is a voltage control circuit for integrated circuits utilizing asynchronous voltage sources that avoids the problems (described above) that are associated with conventional integrated circuits.
The present invention is directed to a voltage control circuit for a non-volatile memory (NVM) array (or other integrated circuit) that couples an output node to the greater of two voltage signals, wherein the voltage control circuit utilizes the gain generated by a comparator circuit to control the coupling process such that the voltage difference needed to switch between the first and second voltage signals is minimized. Specifically, the comparator circuit is constructed to provide an output gain such that a relatively small difference between the first and second voltage signals causes the comparator output signal to switch between a maximum (high) voltage level and a minimum (low) voltage level (e.g., ground). The high or low comparator output signal is transmitted to a switch control circuit, which controls a pair of switches to couple one of the first and second voltage sources to the output node according to the comparator output signal level. Accordingly, the voltage control circuit of the present invention minimizes the range in which small differences between asynchronous voltage sources produce floating output signals, thereby improving the performance of the NVM device and preventing latch-up and coupling of the voltage sources.
In accordance with a specific embodiment of the present invention, the comparator circuit includes a four PMOS transistors respectively connected in series with four NMOS transistors between the two voltage sources and ground. In particular, a first PMOS transistor is connected between the first voltage source and a first NMOS transistor, a second PMOS transistor is connected between the second voltage source and a second NMOS transistor, a third PMOS transistor is connected between the first voltage source and a third NMOS transistor, and a fourth PMOS transistor is connected between the second voltage source and a fourth NMOS transistor. The first and second NMOS transistors are controlled by a bias signal, which is selected to produce a first current through the first PMOS transistor and the first NMOS transistor, and a second current through the second PMOS transistor and the second NMOS transistor. The first and fourth PMOS transistors are connected to a node located between the first PMOS and first NMOS transistors, and the second and third PMOS transistors are connected to a node located between the second PMOS and second NMOS transistors. Finally, the third and fourth NMOS transistors are connected to a node located between the third PMOS and third NMOS transistors. An output node located between the fourth PMOS transistor and the fourth NMOS transistor is connected to an input terminal of the switch control circuit. The switch control circuit includes a pair of series connected inverters and level shifters for controlling the first and second PMOS switches. With this arrangement, when the first voltage signal is greater than the second voltage signal by even a small amount (i.e., significantly less than the threshold voltage of a transistor), the current through the fourth PMOS transistor becomes less than the current through the fourth NMOS transistor, and the output node VOUT is pulled to ground. Conversely, when the first voltage signal is less than the second voltage signal by the small amount, then the current through the fourth PMOS transistor becomes greater than the current through the fourth NMOS transistor, and the output node VOUT is pulled up to the second voltage signal. Accordingly, the voltage control circuit of the present invention avoids the wide voltage range that produces the floating output signal in conventional voltage control circuits.